Department : ASIC
Location : Cairo
Responsibilities :
Experience / Requirements:
Description :
Location : Cairo
Responsibilities :
- Translating schematic-level analog and RF circuits into layout views using Cadence and Mentor tools in a timely fashion.
- Performing post-layout verification (DRC, LVS, etc) and parasitic extractions and debugging such issues.
- Interacting with design team to establish layout requirements and constraints
Experience / Requirements:
- A B.Sc. in Electrical Engineering, with an aptitude to learn and make a career in the area of VLSI layout design.
- Experience in floor-planning, placement, layout, layout verification and parasitic extraction.
- Experience in working with different EDA tools such as Cadence, Cadence Virtuoso, Calibre, and Mentor Graphics.
- Literate in CMOS design kits.
- Shell or SKILL scripts writing experience is a plus.
- Must be self-motivated, and detail-oriented, with excellent communication skills.
Description :
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